1. Field of the Invention
This invention relates to integrated circuit (IC) technology, and more particularly, an ESD (electrostatic discharge) protection circuit with a low triggering voltage and a low leakage current, which is designed for use with a multi-voltage power supply circuit to protect the internal circuitry of the multi-voltage power supply circuit against ESD stress.
2. Description of Related Art
Electrostatic discharge (ESD) is a movement of static electricity from a nonconductive surface, which can easily cause damage to IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry an amount of electrostatic charge up to several thousands of volts under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostaticity on his/her body would be instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit between each neighboring pair of I/O pads on the internal circuitry of the IC package.
One drawback to the prior art, however, is that when the IC device is fabricated at a downsized level of integration, such as the deep-submicron level, the gate-oxide structure will be reduced in thickness. This would cause the breakdown voltage of the gate-oxide structure to become close to or below the breakdown voltage at the source/drain junction, thus degrading the ESD protection capability. The internal circuitry of an IC device is typically designed in accordance with the Minimum Design Rules. Therefore, the various semiconductor components of an IC device are designed to the minimum size. This practice, however, would make some components vulnerable to ESD-induced transient current, such as the edges of the areas extending from the contact windows to the diffusion areas and the areas from the contact windows to the gates, when these components are further downsized. For this reason, a highly-integrated IC device fabricated at the deep-submicron level of integration is particularly vulnerable to ESD. Therefore, in the IC industry, much research effort has been directed to ESD protection in integrated circuitry.
FIGS. 1A-1C are schematic diagrams each showing the circuit configuration of a conventional ESD protection circuit.
FIG. 1A is a schematic diagram showing the circuit configuration of a first conventional ESD protection circuit. As shown, this ESD protection circuit is coupled between the internal circuitry 216 and a bonding pad 210 of an IC device, and which is composed of a NMOS transistor 212 and an PMOS transistor 214. The NMOS transistor 212 is connected in such a manner that its drain is connected to the bonding pad 210; its source is connected to the ground; and its gate is also connected to the ground. The PMOS transistor 214 is connected in such a manner that its drain is connected to the bonding pad 210; its source is connected to a system voltage line VDD; and its gate is also connected to the system voltage line VDD. When ESD occurs at the bonding pad 210, the ESD-induced transient current can be diverted via the NMOS transistor 212 to the ground and also via the PMOS transistor 214 to the system voltage line VDD without flowing into the internal circuitry 216.
FIG. 1B is a schematic diagram showing the circuit configuration of a second conventional ESD protection circuit. As shown, this ESD protection circuit is coupled between the internal circuitry 226 and a bonding pad 220 of an IC device, and which is composed of a pair of NMOS transistors 222, 224. The first NMOS transistor 222 is connected in such a manner that its drain is connected to the bonding pad 220; its source is connected to the ground; and its gate is also connected to the ground. The NMOS transistor 224 is connected in such a manner that its source is connected to the bonding pad 220; its drain is connected to a system voltage line VDD; and its gate is also connected to the bonding pad 220. When ESD occurs at the bonding pad 220, the ESD-induced transient current can be diverted via the first NMOS transistor 222 to the ground and also via the second NMOS transistor 224 to the system voltage line VDD without flowing into the internal circuitry 216.
FIG. 1C is a schematic diagram showing the circuit configuration of a third conventional ESD protection circuit. As shown, this ESD protection circuit is coupled between the internal circuitry 236 and a bonding pad 230 of an IC device, and which is composed of a pair of NMOS transistors 232, 234. This ESD protection circuit differs from the one shown in FIG. 1B only in that here the gate of the second NMOS transistor 234 is connected to the ground rather than to the bonding pad 230. This circuit configuration also can prevent the ESD-induced transient current from the bonding pad 230, if any, from flowing into the internal circuitry 236.
The foregoing three ESD protection circuits all utilize junction breakdown voltage for ESD protection. One drawback to this scheme, however, is that when the IC device is fabricated at a further downsized level of integration, such as the deep-submicron level, the gate-oxide structure will be reduced in thickness, which would cause the gate-oxide structure to be subjected to breakdown prior to the occurrence of the junction breakdown. In this case, the foregoing ESD protection circuits of FIGS. 1A-1C would lose their ESD protection capability.
Therefore, the present design scheme for ESD protection circuit may be unsuitable for use in further-downsized IC devices. For this reason, it is still an research effort in the IC industry for a new ESD protection circuit that can be suited for use with deep-submicron IC technology.
It is therefore an objective of this invention to provide a new ESD protection circuit, which can be suited for use with deep-submicron IC technology.
In accordance with the foregoing and other objectives, a new ESD protection circuit is proposed. The ESD protection circuit of the invention is designed for use with a multi-voltage power supply circuit having a first internal circuit using a first system voltage and a second internal circuit using a second system voltage, with the first internal circuit having a first set of bonding pads and the second internal circuit having a second set of bonding pads. The ESD protection circuit of the invention comprises: (a) a first ESD bus; (b) a first set of ESD protection units each being coupled between the first ESD bus and one of the first set of bonding pads of the multi-voltage power supply circuit, and each of which is capable of being switched on in the event of an ESD stress to the associated one of the first set of bonding pads; (c) a second ESD bus; (d) a second set of ESD protection units each being coupled between the second ESD bus and one of the second set of bonding pads of the multi-voltage power supply circuit, and each of which is capable of being switched on in the event of an ESD stress to the associated one of the second set of bonding pads; and (e) a routing circuit coupled between the first ESD bus and the second ESD bus, which allows an ESD-induced transient current in the first ESD bus to flow to the second ESD bus and an ESD-induced transient current in the second ESD bus to flow to the first ESD bus.
Each of the ESD protection units comprises: (a) a first resistor having a first end and a second end, with the first end being connected to the associated bonding pad; (b) a second resistor having a first end and a second end, with the first end being connected to the associated ESD bus; (c) a PNP transistor whose base is connected to the second end of the first resistor, whose emitter is connected to the bonding pad, and whose collector is connected to the second end of the second resistor; (d) an NPN transistor whose base is connected to the second end of the second resistor, whose collector is connected to the second end of the first resistor, and whose emitter is connected to the ESD bus; and (e) a first set of PMOS transistors which are connected in such a manner that each of which except the first one is connected in such a manner that its source is connected to the drain of the previous PMOS transistor; its drain is connected to the source of the next PMOS transistor; its gate is tied to its drain; and its substrate is tied to its source; while the first PMOS transistor is connected in such a manner that its source is connected to the second end of the first resistor and its substrate is connected to the associated one of the bonding pad; and the last PMOS transistor is connected in such a manner that its drain is connected to the ESD bus.
The foregoing ESD protection circuit of the invention has a low triggering voltage and a low leakage current that allows it to be suitable for use with the multi-voltage power supply circuit to protect the internal circuitry of the multi-voltage power supply circuit against ESD stress. The invention is not only suitable for use with 0.18 xcexcm technology, but also suitable for use with 0.15 xcexcm or 0.13 xcexcm technology, and nevertheless can provide a robust ESD protection capability to the associated IC device.